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1 for more information www.linear.com/lt8495 typical application features description sepic/boost converter with 2a, 70v switch, 9a quiescent current, por and watchdog timer the lt ? 8495 is an adjustable frequency (250khz to 1.5mhz) monolithic switching regulator with a power-on reset and watchdog timer. quiescent current can be less than 9 a when operating and is ~0.3 a when swen, wde and rstin are low. configurable as a sepic, boost or flyback con - verter, the low ripple burst mode operation maintains high efficiency at low output current while keeping output ripple below 10 mv. dual supply pins (v in and bias) allow the part to automatically operate from the most efficient supply. input supply voltage can be up to 60 v for sepic topologies and up to 32v ( with ride-through up to 60v) for boost and flyback topologies. after start-up, battery life is extended since the part can draw current from its output (bias) even when v in voltage drops below 2.5v. the reset and watchdog timeout periods are independently adjustable using external capacitors. using a resistor divider on the swen pin provides a programmable undervoltage lockout ( uvlo) for the converter. a resistor divider connected to rstin provides uvlo control that asserts the rst pin. additional features such as frequency foldback and soft- start are integrated. fault tolerance in the tssop allows for adjacent pin shorts or an open without raising the output voltage above its programmed value. the lt8495 is available in 20- lead qfn and 20- lead tssop packages with exposed pads for low thermal resistance. no-load supply current efficiency 450khz, 5v output sepic converter applications n wide input voltage range of ~1v to 60v (2.5v to 32v for start-up) n low ripple burst mode ? operation n 9a i q at 12v in to 5.0v out n output ripple (<10mv typ .) n dual supply pins: n improves efficiency n reduces minimum supply voltage to ~1v after start-up to extend battery life n integrated 2a/70v power switch n programmable w atchdog timer can operate when v in supply is removed n programmable power-on reset t imer (por) with rst functional for input supply down to 1.3v n fmea fault tolerant in tssop package n fixed frequency pwm , sepic/boost/fl yback topologies n programmable switching frequency: 250khz to 1.5mhz n uvlo programmable on swen and rstin pins n soft-start programmable with one capacitor n small 20-lead qfn or 20-lead tssop packages n automotive ecu power n power for portable products n industrial supplies l , lt , lt c , lt m , linear technology, the linear logo and burst mode are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 2.2f 15h ? 15h 47f 2 1f 4.7nf 1nf v in 3v to 60v v out 5v 0.35a (v in = 3v) 0.6a (v in = 5v) 1.0a (v in >12v) sw bias rstin gnd fb wdo wde rst wdi v in swen cwdt cpor ss rt 1m 8.87k 316k 8495 ta01a 169k c lt8495 ? 4.7pf 2.2f 8495 ta01b 8495 ta01c lt 8495 8495fa 60 0 5 10 15 20 25 supply current (a) v in = 12v v in = 24v watchdog enabled v in = 5v load current (a) 0.0 0.2 0.4 0.6 0.8 1.0 60 65 watchdog disabled 70 75 80 85 90 efficiency (%) input voltage (v) 0 12 24 36 48
2 for more information www.linear.com/lt8495 pin configuration absolute maximum ratings v in , bias voltage ...................................................... 60 v s wen , wde , rstin voltage ..................................... 60 v fb voltage ................................................................. 60 v s w voltage ............................................................... 70 v w di , rst , wdo voltage .............................................. 6 v rt voltage .................................................................. 6 v (note 1) fe package 20-lead plastic tssop 1 2 3 4 5 6 7 8 9 10 top view 20 19 18 17 16 15 14 13 12 11 bias fb fb nc cpor cwdt rst ss nc rt sw nc v in nc wdi wdo gnd wde swen rstin 21 gnd ja = 38c/w exposed pad ( pin 21) is gnd, must be soldered to pcb 20 19 18 17 16 6 7 8 top view 21 gnd uf package 20-lead (4mm 4mm) plastic qfn 9 10 5 4 3 2 1 11 12 13 14 15 ss rt gnd gnd rstin gnd gnd gnd sw gnd rst cwdt cpor fb bias swen wde wdo wdi v in ja = 47c/w exposed pad ( pin 21) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range lt8495euf#pbf lt8495euf#trpbf 8495 20-lead (4mm 4mm) plastic qfn C40c to 125c lt8495iuf#pbf lt8495iuf#trpbf 8495 20-lead (4mm 4mm) plastic qfn C40c to 125c lt8495efe#pbf lt8495efe#trpbf lt8495fe 20-lead plastic tssop C40c to 125c lt8495ife#pbf lt8495ife#trpbf lt8495fe 20-lead plastic tssop C40c to 125c lt8495hfe#pbf lt8495hfe#trpbf lt8495fe 20-lead plastic tssop C40c to 150c consult lt c marketing for parts specified with wider operating temperature ranges. *the temperature grade is identified by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ cpor , cwdt , ss voltage ........................................... 3 v operating junction temperature range lt 849 5 e, lt 8495 i ( notes 2, 3) .......... C 40 c to 125 c lt 849 5 h ( notes 2, 3) ........................ C 40 c to 150 c storage temperature range .................. C 65 c to 150 c lead temperature ( soldering , 10 sec ) fe p ackage ....................................................... 30 0 c lt 8495 8495fa
3 for more information www.linear.com/lt8495 electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = v swen = 12v, v bias = v wde = 5v, unless otherwise noted (note 2). parameter conditions min typ max units minimum v in operating voltages v bias < 2.5v v bias 2.5v l l 2.4 2.5 0 v v minimum bias operating v oltages v in < 2.5v v in 2.5v l l 2.4 2.5 0 v v power switch driver (psd) over voltage threshold (note 4) v in or bias rising v in or bias falling l l 32.1 32 34 33.9 36.5 36.4 v v power switch driver (psd) over voltage threshold hysteresis (note 4) 100 mv quiescent current from v in v swen = 0v, v wde = 0v, v rstin = 0v v swen = 5v, v wde = 0v, v fb = v rstin = 1.25v v swen = 5v, v wde = 5v, v fb = v rstin = 1.25v v swen = 5v, v wde = 0v, v fb = v rstin = 1.25v (lt8495e, lt8495i) (lt8495h) v swen = 5v, v wde = 5v, v fb = v rstin = 1.25v (lt8495e, lt8495i) (lt8495h) l l l l 0.3 3.0 3.1 3.0 3.0 3.1 3.1 0.9 4.8 4.9 6.2 8.0 6.3 8.0 a a a a a a a quiescent current from bias v swen = 0v, v wde = 0v, v rstin = 0v v swen = 5v, v wde = 0v, v fb = v rstin = 1.25v v swen = 5v, v wde = 5v, v fb = v rstin = 1.25v v swen = 5v, v wde = 0v, v fb = v rstin = 1.25v (lt8495e, lt8495i) (lt8495h) v swen = 5v, v wde = 5v, v fb = v rstin = 1.25v (lt8495e, lt8495i) (lt8495h) l l l l 0.07 1.7 6.0 1.7 1.7 6.0 6.0 0.5 2.8 8.5 4.0 11 10.0 15.5 a a a a a a a bias to v in comparator threshold v bias -v in , v bias rising, v in = 12v v bias -v in , v bias falling, v in = 12v hysteresis (rising-falling threshold) l l l 0.55 0.17 0.20 0.90 0.37 0.53 1.2 0.57 0.80 v v v feedback v oltage l 1.178 1.202 1.230 v fb pin bias current (note 7) v fb = 1.202v 0.1 20 na fb voltage line regulation 5v v in 32v, v bias = 5v 5v v in 32v, v bias = 0v 0.2 0.2 10 10 m%/v m%/v minimum switch off-t ime 70 ns minimum switch on-time 95 ns switching frequency r t = 68.1k r t = 324k l l 0.92 219 1.0 250 1.06 280 mhz khz switch current limit at min. duty cycle (note 5) l 2.1 2.55 2.95 a switch current limit at max. duty cycle (note 6) l 1.3 1.85 2.4 a switch v cesat i sw = 1.2a 340 mv switch leakage current (note 7) v sw = 12v, v swen = 0v 0.01 1 a soft-start charging current (note 7) v ss = 100mv l 5.2 8.2 12.2 a swen pin current (note 7) v swen = 1.2v v swen = 5v v swen = 12v 0 35 240 25 200 550 na na na swen rising v oltage threshold l 0.9 1 1.1 v swen voltage hysteresis 30 mv lt 8495 8495fa
4 for more information www.linear.com/lt8495 electrical characteristics the l denotes the specifications which apply over the full operating junction temperature range, otherwise specifications are at t a = 25c. v in = v swen = 12v, v bias = v wde = 5v, unless otherwise noted (note 2). parameter conditions min typ max units rstin pin current (note 7) v rstin = 1.2v v rstin = 5v v rstin = 12v 0 35 240 25 200 550 na na na rstin threshold as % of v fb regulation voltage l 86 92 97 % rstin low to rst asserted (t uv ) step v rstin from 1.3v to 0.9v l 8 23 60 s watchdog timeout and reset delay period (t rst ) (note 8) c por = 4700pf, watchdog timeout not occurring at same time as the reset delay l 8.5 9.5 11.85 ms watchdog upper boundary (t wdu ) (note 8) c wdt = 1000pf l 14.9 16.7 20.9 ms watchdog lower boundary (t wdl ) (note 8) c wdt = 1000pf l 580 650 812 s rst output voltage low i sink = 1.25ma i sink = 100a, v bias = 1.3v, v in = 0v i sink = 100a, v in = 1.3v, v bias = 0v l l l 33 15 15 150 150 150 mv mv mv rst leakage current v rstin = 1.2v, v rst = 5v (lt8495e, lt8495i) v rstin = 1.2v, v rst = 5v (lt8495h) l l 0 0 0.3 1.0 a a wdo output v oltage low i sink = 1.25ma l 120 420 mv wdo leakage current v wdo = 5v l 0 0.25 a wdi pin current v wdi = 5v 0 0.1 a wdi input rising threshold l 0.4 0.8 1.25 v wdi voltage hysteresis 58 mv wdi input pulse width l 300 ns wde pin current (note 7) v wde = 1.2v v wde = 5v v wde = 12v 0 35 240 25 200 550 na na na wde rising v oltage threshold l 0.9 1 1.1 v wde voltage hysteresis 30 mv note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. voltages are with respect to gnd pin unless otherwise noted. note 2: the lt8495e is guaranteed to meet performance specifications from 0c to 125c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the lt8495i is guaranteed to meet performance specifications from C40c to 125c junction temperature. the lt8495h is guaranteed over the full C40c to 150c operating junction temperature range. operating lifetime is derated at junction temperatures greater than 125c. note 3: this ic includes overtemperature protection that is intended to protect the device during momentary overload conditions. junction temperature will exceed the maximum operating range when overtemperature protection is active. continuous operation above the specified maximum operating junction temperature may impair device reliability. note 4: see power supplies and operating limits in the applications information section for more details. note 5: current limit guaranteed by design and/ or correlation to static test. slope compensation reduces current limit at higher duty cycles. note 6: max duty cycle current limit measured at 1mhz switching frequency. note 7: polarity specification for all currents into pins is positive. all voltages are referenced to gnd unless otherwise specified. note 8: this specification is guaranteed for only the exact capacitance as listed in the conditions. variation of the capacitance from the exact listed value will cause proportional variation to t rst , t wdu and t wdl . lt 8495 8495fa
5 for more information www.linear.com/lt8495 typical performance characteristics switching waveforms, full frequency continuous operation switching waveforms, burst mode operation transient load response; load current is stepped from 20ma ( burst mode operation) to 220ma transient load response; load current is stepped from 300ma to 500ma maximum load current no load supply current load regulation t a = 25c, unless otherwise noted. 8495 g01 8495 g02 10ms/div front page application v in = 12v v out = 5v i load = 20ma v sw 10v/div v out 5mv/div i l 0.5a/div 8495 g04 500s/div front page application v in = 12v v out = 5v v out 50mv/div i l 0.5a/div 8495 g06 500s/div front page application v in = 12v v out = 5v v out 100mv/div i l 0.5a/div 8495 g07 1s/div front page application v in = 12v v out = 5v i load = 0.5a v sw 10v/div v out 5mv/div i l 0.5a/div 8495 g05 8495 g08 temperature (c) ?50 0.0 switch current limit (a) 2.5 2.0 1.5 1.0 0.5 3.0 100 150 0 8495 g09 50 switch current limit at 500khz switch current limit at minimum duty cycle lt 8495 8495fa 150 0 20 40 60 80 100 supply current (a) front page application typical front page application minimum v in (v) 0 12 24 36 48 60 0.0 0.5 v in =12v 1.0 1.5 2.0 2.5 load current (a) v in =12v front page application referenced to v out at 100ma load load current (ma) 0 temperature (c) 200 400 600 800 1000 ?0.15 ?0.10 ?0.05 ?0.00 0.05 ?50 0.10 0.15 load regulation (%) lt8495 g03 duty cycle (%) 10 20 30 40 50 ?10 60 70 80 90 0.0 0.5 1.0 1.5 2.0 2.5 30 3.0 switch current limit (a) 70 110
6 for more information www.linear.com/lt8495 typical performance characteristics feedback voltage oscillator frequency frequency foldback minimum switch on-time minimum switch off-time switch v cesat watchdog upper boundary period watchdog lower boundary period overvoltage lockout t a = 25c, unless otherwise noted. switch current (a) 0.0 0 switch v cesat (mv) 500 400 300 200 100 600 1.5 2.0 0.5 8495 g10 1.0 temperature (c) ?50 1.18 fb voltage (v) 1.22 1.21 1.20 1.19 1.23 100 150 0 8495 g11 50 temperature (c) ?50 0.00 frequency (mhz) 1.25 1.00 0.50 0.25 0.75 1.50 100 150 0 8495 g12 50 r t = 68.1k r t = 324k 8495 g13 r t = 68.1k r t = 324k temperature (c) ?50 0 switch on-time (ns) 100 120 80 60 40 20 140 100 150 0 8495 g14 50 temperature (c) ?50 0 switch off-time (ns) 100 120 140 160 80 60 40 20 180 100 150 0 8495 g15 50 temperature (c) ?50 33.0 v in or bias voltage (v) 35.0 34.5 34.0 33.5 35.5 100 150 0 8495 g16 50 v in or bias rising v in or bias falling 8495 g17 temperature (c) ?50 620 lower boundry period t wdl (s) 720 740 700 680 660 640 760 100 150 0 8495 g18 50 c wdt = 1nf tdk c2012cog1h102j lt 8495 8495fa 200 400 600 800 1000 1200 switching frequency (khz) c wdt = 1nf tdk c2012c0g1h102j fb voltage (v) temperature (c) ?50 ?10 30 70 110 150 15 16 17 0.0 18 19 20 upper boundary period, t wdu (ms) 0.2 0.5 0.7 1.0 1.2 0
7 for more information www.linear.com/lt8495 typical performance characteristics reset timeout period t a = 25c, unless otherwise noted. temperature (c) ?50 8 reset timeout period t rst (ms) 11 10 9 12 100 150 0 8495 g19 50 c por = 4.7nf tdk c2012cog1h472j 8495 g20 reset timeout period vs capacitance watchdog lower boundary period vs capacitance watchdog upper boundary period vs capacitance 8495 g21 8495 g22 swen/rstin/wde pin current fb pin current swen/rstin /wde pin voltage (v) 0 0 swen/rstin/wde pin current (na) 250 350 300 200 150 100 50 400 504030 60 10 8495 g23 20 fb voltage (v) 0 0.001 fb pin current (a) 10 100 1 0.1 0.01 1000 504030 60 10 8495 g24 20 rst output voltage vs supply voltage v in /bias voltage (v) 0 0 rst output voltage (v) 2 3 1 3 1 8495 g25 2 10k pull-up from v in to rst internal uvlo temperature (c) ?50 2.30 v in /bias voltage (v) 2.40 2.45 2.50 2.35 150 100 0 8495 g26 50 v in /bias rising v in /bias falling lt 8495 8495fa 1 10 100 1k 10k 100k upper boundary period, t wdu (ms) cpor pin capacitance, c por (nf) 0.01 0.1 cwdt pin capacitance, c wdt (nf) 1 10 100 1000 0.1 1 10 100 1k 10k 0.01 reset timeout period, t rst (ms) cwdt pin capacitance, c wdt (nf) 0.01 0.1 1 10 100 1000 0.01 0.1 0.1 1 10 100 1k lower boundary period, t wdu (ms) 1 10 100 1000 0.1
8 for more information www.linear.com/lt8495 typical performance characteristics t a = 25c, unless otherwise noted. rst pin current vs supply voltage pin current quiescent current v in voltage (v) 0 0 2 4 6 8 10 12 14 16 18 rst pin current (ma) 20 54 21 8495 g27 3 v in = bias = rstin, swen = wde = 0 rst = 0.4v v in = bias, swen = wde = rstin = 0 temperature (c) ?50 0 20 40 current into pin (na) 60 150 50 0 8495 g28 100 v fb = 1.25v v swen = v wde = v rstin = 1.2v i swen = i wde = i rstin i fb temperature (c) ?50 0 6 4 2 8 10 quiescent current (a) 12 150 50 0 8495 g29 100 v in = 12v, v bias = 5v v swen = v wde = 5v v fb = v rstin = 1.25v current into bias current into v in lt 8495 8495fa
9 for more information www.linear.com/lt8495 pin functions (qfn/tssop) ss ( pin 1/pin 8): soft- start pin. place a soft- start capacitor on this pin. upon start-up, the ss pin will be charged by a (nominally) 256k resistor to about 2.1v. rt (pin 2/pin 10): oscillator frequency set pin. place a resistor from this pin to ground to set the internal oscil - lator frequency . minimize capacitance on this pin. see the applications information section for more details. gnd (pins 3, 4, 11, 13, 14, 15, exposed pad 21/pin 14, exposed pad 21): ground. solder all pins and the exposed pad directly to the local ground plane. the exposed pad metal of the package provides both electrical contact to ground and good thermal contact to the printed circuit board. nc (pins 4, 9, 17, 19, tssop only): no connects: these pins are not connected to internal circuitry and must be left floating to ensure fault tolerance. rstin (pin 5/pin 11): reset input reference. connect a resistor divider to rstin to set the threshold voltage for asserting rst . the rstin voltage is compared to an internal 1.1 v reference. rstin voltages lower than the reference cause rst to assert low. swen (pin 6/pin 12): switch enable detect pin. this pin enables/disables the switching regulator and soft-start. a resistor divider can be connected to swen to perform an under voltage lockout function. wde (pin 7/pin 13): watchdog timer enable pin. drive above 1.1 v to enable the watchdog timer function. when wde is low, the wdo output driver is disabled causing the pin to be high impedance. wdo (pin 8/pin 15): watchdog out. active low, open- drain output. wdo asserts low if wde is enabled and the microcontroller fails to drive the wdi pin of the lt8495 with the appropriate signal. wdi (pin 9/pin 16): watchdog timer input pin. this pin receives the watchdog signal from a microcontroller. if the appropriate signal is not received, wdo will pulse low for a period equal to the reset delay timer period (t rst ). v in (pin 10/pin 18): supply input pin. this pin is typically connected to the input of the dc/dc converter. must be locally bypassed. sw (pin 12/pin 20): switch pin. this is the collector of the internal npn power switch. minimize trace area con - nected to this pin to minimize emi. bias ( pin 16/pin 1): supply input pin. this pin is typi- cally connected to the output of the dc/dc converter in cases where v in can be higher than v out . must be locally bypassed. fb (pin 17/pins 2, 3): output voltage feedback pin. the lt8495 regulates the fb pin to 1.202 v. connect a resis - tor divider between the output, fb and gnd to set the regulated output voltage. cpor (pin 18/pin 5): wdo and rst active delay period programming pin. attach an external capacitor (c por ) to gnd to set the period (t rst ). see the applications infor- mation section for more information. cwdt ( pin 19/pin 6): watchdog timer programming pin. place a capacitor (c wdt ) between this pin and ground to adjust the watchdog timer upper (t wdu ) and lower (t wdl ) boundary periods. see the applications information section for more information. rst ( pin 20/pin 7): active low, open - drain reset. asserts low when rstin is less than ~1.1v ( see electrical charac - teristics). after rstin rises, rst will remain asserted low for the period (t rst ) set by the capacitor on the cpor pin. lt 8495 8495fa
10 for more information www.linear.com/lt8495 block diagram + ? + ? v in 2.4v + ? die temp 165c 2.1v 1.10v 1.00v others + ? + ? sw rst wdo bias gnd swen 2.4v 34v 1.00v q 256k s r ovp i limit vc_limiter chip shutdown sr2 r q s sr1 a2 2.1v ss disable psd + ? + ? supply select logic voltage refs burst mode detect quadratic ramp generator adjustable reset pulse generator watchdog timer transition detect watchdog timeout frequency foldback chip shutdown 1.10v low power mode soft- start 34v + ? 100mv 1.202v + ? + ? rt fb wde rstin pgood reset enable 2.3a 23a a3 vc + ? a1 cpor 8495 bd 1.00v + ? 2.3a 23a wdi cwdt power switch driver q1 adjustable oscillator lt 8495 8495fa
11 for more information www.linear.com/lt8495 timing diagrams start-up timing rstin timing watchdog timing, upper boundary 2.4v 1.202v 0.2v 8495 td01 t startup t rst t dw 1.3v v in ss cpor cwdt rst wdo rstin rst 1.1v t uv t rst 8495 td02 t startup = time required to start up the chip, approximately 1ms t dw = time required to start up the watchdog or por timer, approximately 200s t uv = time required to assert rst low after rstin goes below its threshold, approximately 23s t rst = programmed reset period t wdu = watchdog upper boundary period, approximately 31 ramping cycles on cwdt pin t wdl = watchdog lower boundary period, approximately 1 ramping cycle on cwdt pin t wdu wdi wdo cwdt 8495 td03 t rst t wdl t rst t < t wdl wdi 8495 td02a cwdt wdo watchdog timing, lower boundary lt 8495 8495fa
12 for more information www.linear.com/lt8495 operation the lt8495 is a constant - frequency, current mode sepic/ boost / flyback regulator with power- on reset and a watchdog timer. operation can be best understood by referring to the block diagram. the switching regulation, watchdog timer and reset detection functions are con - trolled by the swen, wde and rstin pins respectively. if all three pins are grounded, the part enters shutdown with minimal current drawn from the v in and bias sources. if any of these three pins are driven above their respective thresholds, this part is turned on. switching regulator operation in the block diagram, the adjustable oscillator, with frequency set by the external r t resistor, enables an rs latch, turning on the internal power switch. an amplifier and comparator monitor the switch current flowing through an internal sense resistor, turning the switch off when this current reaches a level determined by the voltage at vc. an error amplifier adjusts the vc voltage by measuring the output voltage through an external resistor divider tied to the fb pin. if the error amplifier s output voltage ( vc) increases, more current is delivered to the output; if the vc voltage decreases, less current is delivered. an active clamp on the vc voltage provides current limit. an internal regulator provides power to the control circuitry. in order to improve efficiency, the npn power switch driver ( see block diagram) supplies npn base current from whichever of v in and bias has the lower supply voltage. however, if either of them is below 2.4 v or above 34v ( typical values), the power switch draws current from the other pin. if both supply pins are below 2.4 v or above 34v then switching activity is stopped. to further optimize efficiency, the lt8495 automatically enters burst mode operation in light load situations. be - tween bursts , all circuitry associated with controlling the output switch is shut down, reducing the v in / bias pin supply currents to be less than 3 a to 6 a typically (see electrical characteristics table). start-up operation several functions are provided to enable a very clean start-up for the lt8495. ? first, the swen pin voltage is monitored by an internal voltage reference to give a precise turn- on threshold. an external resistor divider can be connected from the input power supply to the swen pin to provide a user- programmable undervoltage lock-out function. ? second, the soft- start circuitry provides for a gradual ramp -up of the switch current. when the part is brought out of shutdown, the external ss capacitor is first dis - charged, and then an integrated 256 k resistor pulls the ss pin up to ~2.1 v. by connecting an external capacitor to the ss pin, the voltage ramp rate on the pin can be set. typical values for the soft- start capacitor range from 100nf to 1f. ? finally, the frequency foldback circuit reduces the maximum switching frequency when the fb pin is below 1v . this feature reduces the minimum duty cycle that the part can achieve thus allowing better control of the switch current during start-up. power-on reset and watchdog timer operation the lt8495 has a power-on reset ( por) circuit and a reset timer to assert the rst pin for a minimum amount of time. after initial power up the open- drain rst pin is asserted low for a programmable reset delay time ( see the timing diagrams). during normal operation, the rst pin can also be asserted when either the rstin pin is below its threshold or the chip enters shutdown due to an abnormal condi - tion. after the chip exits shutdown and the rstin pin rises above its threshold, the rst pin is released after the reset delay time which is programmable through the cpor pin. the watchdog timer typically monitors a microcontrollers activity. the watchdog timer can be enabled or disabled by applying a logic signal to the wde pin. when enabled, the watchdog timer requires successive negative edges on the wdi pin to happen within a programmed time win - dow to keep wdo from pulsing low. therefore, if the time between the two negative wdi edges is too short or too long, the wdo pin will be pulsed low. when the wdo pin pulls low, a reset timer keeps the wdo pin low for a delay programmed by the cpor pin. the wdo pin will go high again after the reset timer expires or the chip shuts down ( see the timing diagrams). the window periods can be set through the cwdt pin. lt 8495 8495fa
13 for more information www.linear.com/lt8495 applications information low ripple burst mode operation to enhance efficiency at light loads, the lt8495 regulator enters low ripple burst mode operation keeping the output capacitor charged to the proper voltage while minimizing the input quiescent current. during burst mode operation, the lt8495 regulator delivers single-cycle bursts of cur - rent to the output capacitor with each followed by a sleep period where the output power is delivered to the load by the output capacitor. the quiescent currents of v in /bias are reduced to less than 3 a to 6 a typically during the sleep time (see electrical characteristics table). as the load current decreases towards a no-load condi - tion, the frequency of single current pulses decreases (see figure 1), therefore the percentage of time that the lt8495 operates in sleep mode increases, resulting in reduced average input current and thus high efficiency even at very low loads. by maximizing the time between pulses, the lt8495 qui - escent current is minimized. therefore, to optimize the quiescent current performance at light loads, the current in the feedback resistor divider and the reverse current in the external diode must be minimized, as these appear to the output as load currents. more specifically, during figure 1. switching frequency in burst mode operation the sleep time, the boost converter has the reverse diode leakage current conducting from output to input, while the sepic converter has leakage current conducting from output to ground. use the largest possible feedback resis - tors and a low leakage schottky diode in applications with ultralow q current. in burst mode operation, the burst frequency and the charge delivered with each pulse will not change with output capacitance. therefore, the output voltage ripple will be inversely proportional to the output capacitance. in a typical application with a 47 f output capacitor, the output ripple is about 10 mv and with two 47 f output capacitors the output ripple is about 5mv ( see switching waveforms, burst mode operation in typical performance characteristics section). the output voltage ripple can con - tinue to be decreased by increasing the output capacitance. at higher output loads the lt8495 regulator runs at the frequency programmed by the r t resistor and operates as a standard current mode regulator. the transition between high current mode and low ripple burst mode operation is seamless, and will not disturb the output voltage. chip enable pins the swen, wde and rstin pins are used to enable various portions of the lt8495. the lowest current state is when all three pins are at 0 v which disables all functions of the lt8495. raising any of these pins above their respective input threshold voltages ( see electrical characteristics section) activates the core circuits of the lt8495. start-up of the lt8495 core circuits typically requires about 1ms (see the timing diagram). see the sections enabling the switching regulator, watchdog timer, and reset condi - tions for further details about swen, wde and rstin respectively. enabling the switching regulator the swen pin is used to enable or disable the switching regulator. this pin operates independently of the watch- dog enable ( wde) and the rst control input (rstin ). the rising threshold of swen is typically 1 v, with 30 mv of hysteresis. the switching regulator is disabled by driving the swen pin below this threshold which deactivates the npn power switch. the switching regulator is enabled by 8495 f01 lt 8495 8495fa 100 200 300 400 500 switching frequency (khz) front page application load current (ma) 0.1 1 10 100 1000 0
14 for more information www.linear.com/lt8495 applications information driving swen above its threshold. before active switching begins, the soft-start capacitor is quickly discharged then slowly charged causing a gradual start-up of the regulator. swen can be connected to v in if always on operation is desired, although some current will flow into the swen pin ( see typical performance characteristics) increasing overall bias current of the system. also, a resistor divider can be connected to swen to create an undervoltage lockout function ( see undervoltage lockouts) for more information. setting the output voltage the output voltage is programmed with a resistor divider from output to the fb pin ( r2) and from the fb pin to ground (r1). choose the 1% resistors according to: r2 = r1 v out 1.202 ? 1 ? ? ? ? ? ? note that choosing larger resistors decreases the quiescent current of the application circuits. in low load applications, choosing larger resistors is more critical since the part enters burst mode operation with lower quiescent current. power switch duty cycle in order to maintain loop stability and deliver adequate current to the load, the power npn ( q1 in the block diagram) cannot remain on for 100% of each clock cycle. the maximum allowable duty cycle is given by: dc max = t p ?minimum switch off-time t p 100% where t p is the clock period and the minimum switch off-time ( found in the electrical characteristics) is typi- cally 70ns. conversely , the power npns ( q1 in the block diagram) cannot remain " off for 100% of each clock cycle, and will turn on for a minimum time ( minimum switch on- time) when in regulation. this minimum switch on-time governs the minimum allowable duty cycle given by: dc min = minimum switch on-time t p 100% where t p is the clock period and minimum switch on- time (found in the electrical characteristics) is typically 95ns. the application should be designed such that the operating duty cycle ( dc) is between dc min and dc max . normally, dc rises with higher v out and lower v in . duty cycle equations for both boost and sepic topologies are given below, where v d is the diode forward voltage drop and v cesat is typically 340mv at 1.2a. for the boost topology: dc ? v out ? v in + v d v out + v d ? v cesat for the sepic topology: dc ? v out + v d v in + v out + v d ? v cesat the lt 8495 can be used in configurations where the duty cycle is higher than dc max , but it must be operated in the discontinuous conduction mode or burst mode operation so that the effective duty cycle is reduced. setting the switching frequency the lt8495 uses a constant frequency pwm architecture that can be programmed to switch from 250 khz to 1.5mhz by using a resistor tied from the rt pin to ground. table ?1 shows the necessary r t values for various switching frequencies. table 1. switching frequency vs r t value switching frequency (mhz) r t value (k) 0.25 324 0.4 196 0.6 124 0.8 88.7 1.0 68.1 1.2 54.9 1.4 45.3 1.5 41.2 lt 8495 8495fa
15 for more information www.linear.com/lt8495 inductor selection general guidelines: the high frequency operation of the lt8495 allows for the use of small surface mount inductors. for high efficiency, choose inductors with high frequency core material, such as ferrite, to reduce core losses. to improve efficiency, choose inductors with more volume for a given inductance. the inductor should have low dcr (copper wire resistance) to reduce i 2 r losses, and must be able to handle the peak inductor current without saturat- ing. note that in some applications, the current handling requirements of the inductor can be lower, such as in the sepic topology when using uncoupled inductors, where each inductor only carries a fraction of the total switch current. molded chokes or chip inductors usually do not have enough core area to support peak inductor currents in the 2 a to 3 a range. to minimize radiated noise, use a toroidal or shielded inductor. note that the inductance of shielded types will drop more as current increases, and will saturate more easily. minimum inductance: although there can be a trade-off with efficiency, it is often desirable to minimize board space by choosing smaller inductors. when choosing an inductor, there are two conditions that limit the mini - mum inductance; (1) providing adequate load current, and (2) avoidance of subharmonic oscillation. choose an inductance that is high enough to meet both of these requirements. adequate load current: small value inductors result in increased ripple currents and thus, due to the limited peak switch current, decrease the average current that can be provided to a load (i out ). in order to provide adequate load current, l should be at least: l > dc v in 2 f ( ) i lim ? v out i out v in ? ? ? ? ? ? for boost topologies, or: l > dc v in 2 f ( ) i lim ? v out i out v in ?i out ? ? ? ? ? ? for the sepic topologies. applications information where: l = l1||l2 for uncoupled sepic topology dc = switch duty cycle (see previous section) i lim = switch current limit, typically about 2.35 a at 50% duty cycle ( see the typical performance characteristics section) = power conversion efficiency (typically 85% to 90% for boost and 80% to 85% for sepic at high currents) f = switching frequency negative values of l indicate that the output load current i out exceeds the switch current limit capability of the lt8495. avoiding subharmonic oscillations: the internal slope compensation circuit of lt8495 helps prevent the subhar - monic oscillations that can occur when the duty cycle is greater than 50%, provided that the inductance exceeds a minimum value. in applications that operate with duty cycles greater than 50%, the inductance must be at least: l > v in ? v cesat ( ) 2dc? 1 ( ) 0.76 1.5 dc + 1 ( ) f 1?dc ( ) for boost and coupled inductor sepic, or: l1||l2 > v in ? v cesat ( ) 2dc? 1 ( ) 0.76 1.5 dc + 1 ( ) f 1?dc ( ) for the uncoupled inductor sepic topologies. maximum inductance: excessive inductance can reduce current ripple to levels that are difficult for the current com - parator ( a2 in the block diagram) to cleanly discriminate, thus causing duty cycle jitter and/or poor regulation. the maximum inductance can be calculated by: l max = v in ? v cesat i min(ripple) dc f where l max is l1||l2 for uncoupled sepic topologies and i min(ripple) is typically 150ma. lt 8495 8495fa
16 for more information www.linear.com/lt8495 applications information current rating: finally, the inductor(s) must have a rating greater than its peak operating current to prevent inductor saturation resulting in efficiency loss. in steady state, the peak and average input inductor cur - rents (continuous conduction mode only) is given by: i l1(peak) = v out i out v in + v in dc 2 l1 f i l1(avg) = v out i out v in for the boost and uncoupled inductor sepic topology. for uncoupled sepic topologies, the peak and average currents of the output inductor l2 is given by: i l2(peak) = i out + v out 1?dc ( ) 2 l2 f i l2(avg) = i out for the coupled inductor sepic: i l(peak) = i out 1 + v out v in ? ? ? ? ? ? + v in dc 2 l f i l(avg) = i out 1 + v out v in ? ? ? ? ? ? note: inductor current can be higher during load transients. it can also be higher during short circuit and start-up if inadequate soft-start capacitance is used. thus, i l(peak) may be higher than the switch current limit of 2.95 a, and the rms inductor current is approximately equal to i l( avg ) . choose an inductor having sufficient saturation current and rms current ratings. capacitor selection low esr ( equivalent series resistance) capacitors should be used at the output to minimize the output ripple voltage. multilayer ceramic capacitors are an excellent choice, as they have an extremely low esr and are available in very small packages. x5r or x7r dielectrics are preferred, as these materials retain their capacitance over wider voltage and temperature ranges. always use a capacitor with a sufficient voltage rating. many capacitors rated at 2.2f to 20 f, particularly 0805 or 0603 case sizes, have greatly reduced capacitance at the desired output voltage. solid tantalum or os-con capacitors can be used, but they will occupy more board area than a ceramic and will have a higher esr with greater output ripple. ceramic capacitors also make a good choice for the input decoupling capacitor, which should be placed as closely as possible to the v in and bias pins of the lt8495. a 2.2f to 4.7 f input capacitor is sufficient for most applications. audible noise ceramic capacitors are small, robust and have very low esr. however, due to their piezoelectric nature, ceramic capacitors can sometimes create audible noise when used with the lt8495. during burst mode operation, the lt8495 regulator s switching frequency depends on the load current, and at very light loads the regulator can excite the ceramic capacitor at audio frequencies, generating audible noise. since lt8495 operates at a lower current limit during burst mode operation, the noise is typically very quiet. if this is unacceptable, use a high performance tantalum or electrolytic capacitor at the output. diode selection the diode used in boost or sepic topologies conducts cur - rent only during switch off- time. during switch on- time, the diode has reverse voltage across it. the peak reverse voltage is equal to v out in the boost topology and equal to ( v out + v in ) in the sepic topology. use a diode with a reverse volt - age rating greater than the peak reverse voltage. an additional consideration is the reverse leakage current. the leakage current appears to the output as load current and affects the efficiency, most noticeably, under light load conditions. in burst mode operation, after the inductor cur - rent vanishes, the reverse voltage across the boost diode is approximately equal to v out C v in in the boost topology and v out in the sepic topology. the percentage of time that the diode is reverse biased increases as load current decreases. schottky diodes that have larger forward voltages often have less leakage, so a trade- off exists between light load and high load efficiency. also the schottky diodes with larger reverse bias ratings may have less leakage at a given output voltage, therefore, superior leakage performance can be lt 8495 8495fa
17 for more information www.linear.com/lt8495 applications information achieved at the expense of diode size. finally, keep in mind that the leakage current of a power schottky diode goes up exponentially with junction temperature. therefore, the schottky diode must be selected with care to avoid excessive increase in light load supply current at high temperatures. soft-start the lt8495 contains a soft-start circuit to limit peak switch currents during start-up. high start-up current is inherent in switching regulators since the feedback loop is saturated due to v out being far from its final value. the regulator tries to charge the output capacitor as quickly as possible, which results in large peak currents. the start-up current can be limited by connecting an external capacitor (typically 100 nf to 1 f) to the ss pin. this capacitor is slowly charged to ~2.1 v by an internal 256 k resistor once the part is activated. ss pin voltages below ~0.8 v reduce the internal current limit. thus, the gradual ramping of the ss voltage also gradually increases the current limit as the capacitor charges. this, in turn, allows the output capacitor to charge gradually toward its final value while limiting the start-up current. when the switching regula - tor shuts down the soft-start capacitor is automatically discharged to ~100 mv or less before charging resumes, thus assuring that the soft-start occurs after every reac - tivation of the switching regulation. power supplies and operating limits the lt8495 draws supply current from the v in and bias pins. the largest supply current draw occurs when the switching regulator is enabled ( swen is high) and the power switch is toggling on and off. under light load condi - tions the switching regulator enters burst mode operation where the power switch toggles infrequently and the input current is significantly reduced ( see the low ripple burst mode operation section). power switch driver ( psd) operating range: the npn power switch is driven by a power switch driver ( psd) as shown in the block diagram. the driver must be powered by a supply (v in or bias) that is above the minimum op- erating voltage and below the psd overvoltage threshold. these voltages are typically 2.4 v and 34 v respectively ( see electrical characteristics). if neither v in nor bias is within this operating range, the psd and the switching regulator are automatically dis- abled. voltages up to 60 v are not harmful to the psd, how - ever, as discussed, switching regulation is automatically disabled when neither v in nor bias is in the valid operating range. see table 2 for some example operating conditions. reset and watchdog operating voltage limits: the reset circuits operate properly as long as either v in or bias is above 1.3 v ( see reset conditions section). the watchdog timer operates properly when either v in or bias is between 2.5 v and 60 v. the table below gives some example operating conditions. table 2: operating condition examples v in (v) bias (v) reset circuits watchdog switching regulator 0 1.3 x 1.3 0 x 1 40 x x 40 40 x x 1 30 x x x 12 40 x x x automatic power supply selection: in order to minimize power loss, the lt8495 draws as much of its required cur- rent as possible from the lowest suitable voltage supply ( v in or bias) in accordance with the requirements described in the previous two sections. this selection is automatic and can change as v in and/or bias voltages change. the lt8495 compares the v in and bias voltages to de- termine which is lower. the comparator has an offset and hysteresis as shown in the electrical characteristics section. the voltage comparison happens continuously when the power switch is toggling. the result of the latest comparison is latched inside the lt8495 when switching stops. if the power switch is not toggling, the lt8495 uses the last v in vs bias comparison to determine which sup- ply is lower. after initial power up or any thermal lockout the lt8495 always concludes that v in is the lower supply voltage until subsequent voltage comparisons can be made while the power switch is toggling. bias connection for sepic converters: for sepic con- verters, where v in can be above or below v out , bias is typically connected to v out which improves efficiency when lt 8495 8495fa
18 for more information www.linear.com/lt8495 applications information v in voltage is higher than v out . connecting bias to v out in a sepic topology also allows the switching regulator to operate with v in above 34v ( typical switch driver overvolt - age threshold ) in cases where v out is regulated below the psd overvoltage threshold. finally, connecting bias to v out also allows the converter to operate from v in voltages less than 2.5 v after v out rises within the psd operating range. this can be very useful in battery powered applications since the battery voltage drops as it discharges. bias connection for boost converters: for boost con- verters, bias is typically connected to v out or to ground. connecting bias to v out allows the converter to operate with v in < 2.5 v after v out has risen within the psd operat- ing range . however, during no load conditions on v out , despite v in being selected as the primary input supply, the overall power loss will be slightly elevated due to the small amount of current still being drawn from the higher voltage bias pin. to minimize boost converter power loss during no load conditions, connect bias instead to ground. for boost applications with v out higher than the psd oper - ating range , the bias pin should not typically be connected to v out . the lt8495 will never draw the majority of its current from bias due to the excessive voltage, therefore this connection does not help to improve efficiency. al - ternative choices for the bias pin connection are ground or another supply that is within the psd operating range. maximum v in for boost converters: v in cannot generally be higher than v out in boost topologies because of the dc path from v in to v out though the inductor and the output diode. if v in must be higher than v out , then the inductor must be powered by a separate supply that is always below v out . otherwise a sepic topology can be used. also, the lt8495 will not operate in a boost topology with v in voltages above the psd operating range unless bias is connected to an alternative supply within the valid operating range. v in / bias ramp rate: while initially powering a switching converter application, the v in / bias ramp rate should be limited. high v in / bias ramp rates can cause excessive in- rush currents in the passive components of the converter. this can lead to current and/ or voltage overstress and may damage the passive components or the chip. ramping rates less than 500mv/s , depending on component parameters, will generally prevent these issues. also, be careful to avoid hot plugging. hot plugging occurs when an active voltage supply is instantly connected or switched to the input of the converter. hot plugging results in very fast input ramp rates and is not recommended. finally, for more information, refer to linear application note 88, which discusses voltage overstress that can occur when inductive source impedance is hot plugged to an input pin bypassed by ceramic capacitors. watchdog timer the lt8495 includes an adjustable watchdog timer that can monitor a microcontroller activity. if a code execution error occurs, the watchdog timer can detect this and pull the open drain wdo pin low. wdo can be connected to rst or to another input of the microcontroller to reset or interrupt the microcontroller. note that the pull-up resis - tor must be connected to wdo for proper operation. this resistor is often already integrated in the microcontroller. the watchdog circuitry monitors negative edges on the wdi pin. the wdi pin s negative going pulses are restricted to appear inside a programmed time window to prevent wdo from going low. during a code execution error, the microcontroller will generate wdi pulses that are either too fast or too slow which will cause wdo to assert low and force the microcontroller to reset the program ( see the timing diagram section). while monitoring wdi, if the time between any two falling edges is shorter than the watchdog lower boundary, t wdl (see figure 2), or longer than the watchdog upper bound- ary, t wdu ( see figure 3), wdo is pulled down for a pro- grammable period of t rst ( see reset conditions section). figure 2. window watchdog waveforms 2ms/div wdi 5v/div wdo 5v/div cwdt 1v/div t wdl = 5.2ms, c wdt = 10nf cpor 1v/div 8495 f02 lt 8495 8495fa
19 for more information www.linear.com/lt8495 applications information figure 3. timeout watchdog waveforms thus, the wdi period should be higher than t wdl , and lower than t wdu to keep wdo high under normal condi- tions. wdo also pulls low if no negative wdi edge occurs during the watchdog upper boundary period. figure 5. watchdog lower boundary parameter figure 4. watchdog upper boundary parameter figure 6. upper and lower boundary ratio 50ms/div wdi 2v/div wdo 5v/div cwdt 1v/div t wdu = 155ms, c wdt = 10nf t rst = 93ms, c por = 47nf cpor 1v/div 8495 f03 8495 f04 8495 f05 8495 f06 selecting the watchdog timing capacitor: the watch- dog timeout period is adjustable and can be optimized for software execution. the watchdog upper and lower boundary timeout periods ( t wdu and t wdl ) are adjusted by connecting a capacitor, c wdt , between the cwdt pin and ground. t wdu is typically 30 ? t wdl for large c wdt values ( greater than about 50 nf). for lower values this ratio reduces as shown in figure 6. to program the t wdu and t wdl periods, see the watchdog upper and lower boundary periods vs capacitance graphs in the typical characteristics section to select c wdt . the required capacitor value can also be calculated from a given watchdog timeout period by using the following equation: c wdt = k 1 ? t wdu where c wdt is the external capacitor value in nf, t wdu is the upper boundary period in ms, and k1 is their ratio with typical values shown in figure 4. k1 can be approximated as 0.065nf/ms for upper boundaries greater than 50ms. in addition, the following equation can be used to calculate the watchdog lower boundary period for a given c wdt capacitor value. t wdl = k2 ? c wdt where t wdl is the lower boundary in ms, c wdt is the external capacitance in nf, and k2 is their ratio with typi- cal values shown in figure 5. k2 can be approximated as 0.52ms/nf for c wdt values greater than 10nf. lt 8495 8495fa 0.040 0.046 0.052 0.058 0.064 0.070 k1 (nf/ms) cwdt pin capacitance, c wdt (nf) 0.01 0.1 upper boundary period, t wdu (ms) 1 10 100 1k 0.4 0.7 1.0 1.3 1.6 k2 (ms/nf) 0.1 cwdt pin capacitance, c wdt (nf) 0.01 0.1 1 10 100 1k 16 20 24 1 28 32 k3 10 100 1k 10k 0.034
20 for more information www.linear.com/lt8495 applications information figure 7. watchdog monitoring the watchdog lower boundary period (t wdl ) has a fixed relationship to t wdu for a given c wdt capacitance. the t wdl period is related to t wdu by the following relationship: t wdu = k3 ? t wdl where k3 is the ratio between upper and lower boundary with typical values shown in figure 6. leaving the cwdt pin unconnected will generate a mini - mum watchdog timeout of approximately 270s . maximum timeout is limited by the largest available low leakage capacitor. the electrical characteristics section indicates the guaranteed tolerance of the timeout period for a given capacitance. the accuracy of the timeout period will also be affected by capacitor leakage ( the nominal charging current is 2.3 a) and capacitor tolerance. a low leakage ceramic capacitor is recommended. watchdog timer start-up: there are several conditions when the wdi pin is not monitored by the watchdog timer. for each condition, the start-up or resumption of wdi pin monitoring occurs as described below: ? the watchdog timer is disabled during the por or thermal lockout. after por and thermal lockout are cleared, cwdt will begin ramping from 0 v. the wdi edges are ignored while the cwdt charges from 0 v to ~200mv . ? the watchdog is disabled when wde is low. after wde rises, cwdt may require 1 s to 100s ( typical) before starting to ramp up . the wdi edges are ignored until the cwdt charges from 0v to ~200mv. ? wdi edges are not monitored while wdo is asserted low. four cpor cycles are required before wdo is released and cwdt begins ramping up. the wdi edges are ignored until the cwdt charges from 0 v to ~ 200mv. if desired, the rst pin can be connected to wde to enable the watchdog timer at about the same time rst is released. for the example shown in figure 7, rst is connected to wde. after the chip starts up, the output voltage ramps up towards 5 v for the microcontroller supply. when v out rises above 4.5v , and thus rstin rises above 1.1v , the rst and wde pins will be held low for the additional period of + ? 1.10v rst wde cpor lt8495 cwdt wdi 8495 f07 wdo rstin 1.00v 374k v out 121k rst wdo wdi v dd c watchdog timer por timer + ? t rst . after t rst , rst is released and wde will pull high, thus enabling the microcontroller and the watchdog timer at about the same time. reset conditions the lt8495 has three reset conditions as described below . all of these conditions can cause the open-drain rst pin to pull low, as long as either v in or bias is above 1.3 v. a pull-up resistor can be connected to the rst pin so that it can be used as a reset for an external microcontroller or other devices. an adjustable timer delays the release of rst by t rst to ensure adequate reset duration for the external devices. the three reset conditions are as follows: ? por: the rst pin is asserted if v in and bias are both below 2.4v ( typical). this is the power-on reset con- dition which causes rst to assert upon initial power up of the lt8495 ( see timing diagrams). under this condition the switching regulator and watchdog timer are disabled and the c wdt , c por , and ss capacitors are discharged to ground. ? thermal lockout: an overtemperature condition on the lt8495 die will cause the rst pin to assert low. see high temperature considerations section for ad- ditional information . this condition disables the switch- ing regulator , the watchdog timer and discharges the c wdt , c por , and ss capacitors to ground. see thermal lockout section for additional information. lt 8495 8495fa
21 for more information www.linear.com/lt8495 applications information ? rstin undervoltage lockout: the open-drain rst pin is asserted low if the rstin input is below the 1.1v typical threshold ( see electrical characteristics). this function enables the use of an external resistor divider to configure an under voltage detection circuit. this reset condition has no effect on the switching regulator or the watchdog timer. see the undervoltage lockouts section for more information. a programmable timer delays the release of rst by t rst after all of the above reset conditions are no longer met. before releasing rst , the external c por capacitor ramps up and down for four cycles creating the t rst delay (see figure 8). to program the t rst period, see the reset timeout period vs capacitance graphs in the typical char- acteristics section to select c por . the required capacitor value can also be calculated from a given reset timeout period by using the following equation: c por = k4 ? t rst where c por is the external capacitor value in nf. t rst is the reset timeout period in ms, and k4 is their ratio with typical values shown in figure 9, k 4 can be approximated as 0.51nf/ ms for reset timeout periods greater than 15 ms. as described previously, this same timer is used to determine how long wdo is asserted low during a watchdog timeout. as an example, to create a 9.5 ms t rst timeout period, choose a c por capacitor value of 4.7 nf. leaving the c por pin unconnected will generate a t rst period of approximately 40 s. the maximum period is limited by the largest available low leakage capacitor. the electrical characteristics section indicates the guaranteed toler - ance of the timeout period for a given capacitance. the accuracy of the timeout period will also be affected by capacitor leakage ( the nominal charging current is 2.3a) and capacitor tolerance. a low leakage ceramic capacitor is recommended. as discussed previously, wdo is asserted low for a pe - riod of t rst after a watchdog error occurs. this period is measured by counting four cycles on the cpor pin in the same way that the reset delay is measured. if a watchdog timeout occurs at the same time as the reset delay period, the watchdog takes priority in the counter. therefore, wdo is always asserted low for four cycles of the cpor pin, while the rst delay may be extended beyond four cycles to a maximum of six cycles, thus increasing t rst by up to 50%. finally note that the t rst delay on the rst pin does not affect the switching regulator or watchdog timer. the switching regulator and/or watchdog timer will start right after the part is no longer in the por or thermal lockout condition. undervoltage lockouts undervoltage lockout ( uvlo) functions can be imple - mented using the swen and/or rstin pins. an under- voltage lockout can shut down appropriate circuitry to prevent undesired operation when input and/or output voltages are too low. figure 8. reset timer waveforms figure 9. reset timer parameter 20ms/div rstin 5v/div rst 5v/div t rst = 93ms, c por = 47nf cpor 500mv/div 8495 f08 8495 f09 lt 8495 8495fa 0.4 0.5 0.6 k4 (nf/ms) reset timeout period, t rst (ms) 0.1 1 10 100 1k 0.2 0.3
22 for more information www.linear.com/lt8495 applications information + ? 2.1v lt8495 1.00v ss 8495 f10 swen 256k r3 487k r4 1m v c v in figure 10. v in undervoltage lockout input uvlo: connecting a resistor divider from v in to swen (see figure 10) implements an input undervoltage lockout circuit. swen has an accurate rising threshold of 1.0v with 30 mv of hysteresis ( typicalCsee electrical specifica - tions). by connecting a resistor divider from v in to swen, the lt8495 will be programmed to disable the switching regulator when v in drops below a desired threshold. typi- cally, this threshold is used in situations where the input supply is current limited, or has a relatively high source resistance. a switching regulator draws constant power from the source, so source current increases as source voltage drops. this looks like a negative resistance load to the source and can cause the source to current limit or latch low under low source voltage conditions. the input uvlo prevents the regulator from operating at source voltages where the problems might occur. as shown in figure 10, by connecting a resistor divider from v in to swen, the falling undervoltage lockout thresh - old is set to: v in(uvlo) = r3 + r4 r3 0.97v from the previous equation, the resistor divider shown in figure 10 gives the v in pin a falling undervoltage lockout threshold of 2.96 v. when v in is below this threshold, the switching regulation is disabled and the ss pin starts to discharge. after choosing the value of r3, for example, r4 can be calculated using: r4 = r3 v in(uvlo) 0.97 ? 1 ? ? ? ? ? ? figure 11. rstin reset lockout + ? + ? 2.3a 23a 8495 f11 1.202v 1.10v vc fb v out r1 316k r2b 1m lt8495 rstin cpor en v dd c c por v out rst por timer r2a 8.87k output uvlo: connecting the rst and rstin pins as shown in figures 11 and 12 implements an output under- voltage lock out ( uvlo) circuit. this circuit resets v out powered devices when v out is below a desired voltage by asserting the open drain rst pin low. note that a pull-up resistor is required on the rst pin, but might already be integrated in the c. there is typically a 23 s delay from the rstin pin falling edge until rst is asserted low (see electrical characteristics section) for glitch immunity of the rstin pin. after rstin rises above its threshold, rst continues to be asserted low for a delayed time program - mable by the cpor pin capacitor. as shown in figure 12, the r2 resistor ( calculated in the setting the output voltage section) is divided into two re - sistors, r2a & r2b to implement the uvlo function. next, the following equations are used to calculate their values. r2a = r1 92% uvlo% nom ? 1 ? ? ? ? ? ? r2b = r2 ?r2a where uvlo% nom is the desired nominal uvlo threshold voltage as a percentage of the nominal v out . uvlo% nom is recommended to be 89.5% or less for most applications. continue reading for more information about selecting uvlo% nom . lt 8495 8495fa
23 for more information www.linear.com/lt8495 applications information when choosing uvlo% nom , consider that the transient response to v out load current steps may cause undershoot of v out . excessive v out undershoot can cause rstin to drop below the comparator threshold and activate rst . the following equation includes the maximum rstin comparator threshold (97% of the fb reference - see electrical character - istics) to show what the maximum uvlo threshold can be. uvlo% max = uvlo% nom 97 92 for example , when choosing uvlo% nom = 89.5%, uvlo% max = 94.36% of v out . therefore the rst pin may assert if v out undershoots more than 5.64% below its steady- state regulated voltage. choose a lower uvlo% nom if more margin is required. in addition, the choice of uvlo% nom affects the minimum possible v out voltage before rst is asserted. uvlo% min = uvlo% nom 86 92 for example , when using uvlo% nom = 89.5%, uvlo% min = 83.66% of v out . therefore the rst pin may not assert unless v out is 16.34% below its nominal value. note that in terms of absolute v out uvlo voltage one must also consider the tolerance of the fb regulation voltage and the r1, r2a and r2b resistor tolerances. in the example shown in figure 11, v out is regulated to 5v. for a desired uvlo% of 89.5%, the calculated r1, r2a , and r2b values are 316k , 8.87k , and 1 m respectively. por uvlo: when both v in and bias are too low for proper lt8495 operation ( typically <2.4v ), the switching regulator and watchdog timers are disabled. for more information see the reset conditions section. high temperature considerations for higher ambient temperatures, care should be taken in the layout of the pcb to ensure good heat sinking of the lt8495. the exposed pad on the bottom of the package must be soldered to a ground plane. this ground should be tied to large copper layers below with thermal vias; these layers will spread heat dissipated by the lt8495. placing additional vias can reduce thermal resistance further. the maximum load current should be derated as the ambient temperature approaches the maximum junction rating. power dissipation within the lt8495 is estimated by calculating the total power loss from an efficiency measurement and subtracting the diode loss, fb resistor loss and inductor loss. the die temperature is calculated by multiplying the lt8495 power dissipation by the thermal resistance from junction to ambient. the power switch and its driver dissipate the most power in the lt8495 ( see block diagram). higher switch cur - rent, duty cycle and output voltage result in higher die temperature. power loss in the power switch driver also increases with higher input supply voltage. the psd is supplied by the lowest suitable voltage on v in and bias. connecting bias to a low voltage supply, often v out , can reduce the maximum die temperature of the lt8495 ( see automatic power supply selection section). also note that leakage current into the swen, rstin, wde, and fb pins increases at high junction temperatures (see typical performance characteristics). the potential leakage current should be considered when choosing high value resistors connected to those pins. thermal lockout: if the die temperature reaches approxi - mately 165 c, the part will go into thermal lockout and the chip will be reset. the part will be enabled again when the die temperature has dropped by ~5c ( nominal). see the reset conditions section for more details about the chips state during thermal lockout fault tolerance the lt8495 is designed to tolerate single fault condition in the tssop package. shorting two adjacent pins together or leaving one single pin floating does not raise v out or cause damage to the lt8495 regulator. figure 12. rstin pin connection options v out r2b r2a rstin r1 fb 8495 f12 v out r2 r1 fb lt 8495 8495fa
24 for more information www.linear.com/lt8495 applications information table 3 and table 4 show the effects that result from short- ing adjacent pins and from a floating pin, respectively. the nc pins must be left floating to ensure fault tolerance. for the best fault tolerance to inadvertent adjacent pin shorts, the bias pin must be tied to something higher than 1.230 v or to the output to avoid overvoltage during a short from fb to bias. table 3. effects of pin shorts (tssop) pin names pin # effect on output fb-bias 1-2 output voltage will fall to approximately 1.202v if bias is connected to the output. cpor-cwdt 5-6 no effect on output. cwdt-rst 6-7 no effect on output. rst -ss 7-8 no effect or output will fall below regulation. rstin -swen 11-12 no effect on output. swen-wde 12-13 no effect on output. wde-gnd 13-14 no effect on output. gnd-wdo 14-15 no effect on output. wdo -wdi 15-16 no effect on output. table 4.effects of floating pins (tssop) pin name pin # effect on output bias 1 depending on the v in voltage and the circuit topology, floating this pin will degrade de- vice performance or the output will fall below regulation. fb 2-3 no effect if the other fb pad is soldered. cpor 5 no effect on output. cwdt 6 no effect on output. rst 7 no effect on output. ss 8 no effect after part has started. can potentially lead to an increase of inrush current during start-up. rt 10 output may fall below regulation. rstin 11 no effect on output. swen 12 enable state of the pin becomes undefined. output will not exceed regulation voltage. wde 13 no effect on output. gnd 14 no effect if exposed pad is soldered. wdo 15 no effect on output. wdi 16 no effect on output. v in 18 depending on the bias voltage and the circuit topology, floating this pin will degrade device performance or the output will fall below regulation. sw 10 output will fall below regulation voltage. exposed pad 21 output maintains regulation, but potential degradation of device performance. layout hints as with all high frequency switchers, when considering layout, care must be taken to achieve optimal electrical, thermal and noise performance. one will not get adver - tised per formance with a careless layout. for maximum efficiency, switch rise and fall times are typically in the 5ns to 10 ns range. to prevent noise, both radiated and conducted, the high speed switching current paths, shown in figures 13 & 14, must be kept as short as possible. this is implemented in the suggested pcb layouts in figures 15 & 16 . shortening this path will also reduce the parasitic trace inductance. at switch-off, this parasitic inductance produces a flyback spike across the lt8495 switch. when operating at higher currents and output volt - ages, with poor layout, this spike can generate voltages across the lt8495 that may exceed its absolute maxi- mum rating . a ground plane should also be used under the switcher circuitry to prevent interplane coupling and overall noise. the fb components should be kept as far away as practical from the switch node. the ground for these components should be separated from the switch current path. failure to do so can result in poor stability or subharmonic oscillation. figure 13. high speed chopped switching path for boost topology figure 14. high speed chopped switching path for sepic topology 8495 f13 v in c1 c2 load l1 sw gnd lt8495 d1 v out high frequency switching path 8495 f14 ? v in c1 c2 c3 load l1 l2 sw gnd lt8495 d1 v out ? high frequency switching path lt 8495 8495fa
25 for more information www.linear.com/lt8495 applications information vias to ground plane c1 d1 c2 v out fb sw wdi wde swen gnd wdo rstin rstin v in 21 cpor cwdt ss rt rst l1 8495 f15 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 vias to ground plane ? ? c1 d1 c3 v out fb sw wdi wde swen gnd wdo rstin rstin v in 21 cpor cwdt ss rt rst c2 l2 l1 8495 f16 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 figure 15. suggested component placement for boost topology. pin 21 (exposed pad) must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance figure 16. suggested component placement for sepic topology. pin 21 (exposed pad) must be soldered directly to the local ground plane for adequate thermal performance. multiple vias to additional ground planes will improve thermal performance lt 8495 8495fa
26 for more information www.linear.com/lt8495 typical applications 750khz, 16v to 32v input, 48v output, 0.5a boost converter efficiency, v in = 24v transient response with 400ma to 500ma to 400ma output load step start-up waveforms v in 16v to 32v v in swen cpor cwdt ss c1: 2.2f, 50v, x5r, 1206 l1: wrth lhmi 74437349220 d1: onsemi mbra2h100 c2: 4.7f, 100v, x7r, 1210 fb sw bias gnd wde lt8495 wdi rstin wdo rst rt c1 2.2f d1 l1 22h v out 48v 0.5a c2 4.7f 2 25.5k 715 8495 ta02 c 1m 10pf 93.1k 0.2f 1nf 4.7nf 8495 ta02b 200ms/div v out 0.5v/div ac coupled i l 0.5a/div 8495 ta02c v in = 24v 5ms/div 96 load v in = 24v v out 20v/div v ss 0.5v/div i l 0.5a/div 8495 ta02d lt 8495 8495fa 75 80 85 90 95 100 efficiency (%) load current (ma) 0 100 200 300 400 500 70
27 for more information www.linear.com/lt8495 typical applications wide input and output range sepic converter with charge pump switches at 400khz v in 6v to 38v (6v to 32v for start-up) wde lt8495 wdi wdo rst d1 d2 d3 d4 1m d6 d5 78.7k 26.7k 1k output adjust 0.1v to 3.2v d7 c8 10f 2 c7 10f 2 c1 2.2f c4 4.7nf c5 1nf 196k 1f c2 10f 2 c10 10f c9 10f c3 3.3f r1 1.2 l1 22h l2 22h v out 20v to 60v 80ma 8495 ta03 c fb bias gnd rstin v in swen cpor cwdt ss sw rt dac l1, l2: coilcraft msd1260t-223ml c1: 2.2f, 50v, x5r,1206 c3: 3.3f, 100v, x7r, 1210 c2, c7-c10: taiyo yuden gmk325c7106kmht, 10f, 35v, x7s, 1210 c4: 4.7nf, 25v, np0, 0603 c5: 1nf, 25v, np0, 0603 d1-d4: fairchild mbr0540 d5-d7: on-semi mbra2h100 r1: 1.2, 0.5w, smd, 2010 (set dac to 3.2v for start-up) lt 8495 8495fa
28 for more information www.linear.com/lt8495 typical applications li-ion to 12v, low q current boost @ 650khz efficiency, v in = 3.3v v in 2.8v to 4.1v v in swen cpor cwdt ss c1: 4.7f, 6.3v, x7r, 1206 c2: 47f, 16v, x5r, 1210 d1: onsemi mbrm120lt1g l1: wrth 74437346068 fb sw gnd wde lt8495 wdi rstin wdo rst rt bias c1 4.7f d1 l1 6.8h v out 12v 200ma c2 47f 110k 3.09k 8495 ta04 c 1m 10pf 113k 1f 1nf 4.7nf 8495 g17 lt 8495 8495fa 65 70 75 80 85 90 95 efficiency (%) load current (ma) 0.2 1 10 100 200 55 60
29 for more information www.linear.com/lt8495 low q current, 5v to 300v, 250khz flyback converter ? ? v in 5v c1 2.2f v in swen cpor cwdt ss c1: 2.2f, 25v, x5r, 1206 c2: tdk c3225ch2j223k d1: vishay gsd2004s dual diode connected in series d2: onsemi mbra2h100 t1: we ?flex transformer 749196121 fb sw gnd wde lt8495 wdi rstin wdo rst rt bias t1 1:5 14.7h d2 d1 v out 300v 2ma c2 22nf keep maximum output power at 0.6w 12.1k 8495 ta05 c 1m 340 1m 1m 324khz 1f 1nf 4.7nf typical applications danger high voltage! operation by high voltage trained personnel only 5ms/div i primary 0.5a/div v out 50v/div 8495 ta05b 2ma load 2s/div 2ma load i primary 1a/div v out 0.5v/div 8495 ta05c start-up waveforms switching waveforms lt 8495 8495fa
30 for more information www.linear.com/lt8495 450khz, 5v output sepic converter (same as front page application) 1.5mhz, 12v output sepic converter efficiency, v in = 12v typical applications v in 3v to 60v v in swen sw bias cpor cwdt c1, c3: 2.2f, 100v, x5r, 1206 c2: taiyo yuden, emk325bj476mm-t d1: onsemi mbra2h100 l1, l2: coiltronics drq125-150-r fb gnd wde lt8495 wdi rstin wdo rst ss rt c1 2.2f c3 2.2f d1 l1 15h l2 15h v out 5v 0.4a (v in = 3v) 0.6a (v in = 5v) 1.0a (v in > 12v) c2 47f 2 316k 8495 ta07 c 1m 8.87k 4.7pf 169k 1nf 1f 4.7nf v in 9v to 16v v in swen sw bias cpor cwdt c1, c3: 2.2f, 50v, x5r, 1206 c2: taiyo yuden, tmk325bj106mm d1: central semi cmmsh2-40 l1, l2: coiltronics drq74-4r7 fb gnd wde lt8495 wdi rstin wdo rst ss rt c1 2.2f c3 2.2f d1 l1 4.7h l2 4.7h v out 12v 0.5a c2 10f 2 110k 8495 ta08a c 1m 3.09k 47pf 41.2k 1nf 1f 4.7nf lt 8495 8495fa 500 50 55 60 65 70 75 80 85 90 power loss 0 300 8495 ta08b 600 900 1200 efficiency (%) power loss (mw) efficiency load current (ma) 0 100 200 300 400
31 for more information www.linear.com/lt8495 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. fe20 (cb) tssop rev k 0913 0.09 ? 0.20 (.0035 ? .0079) 0 ? 8 0.25 ref recommended solder pad layout 0.50 ? 0.75 (.020 ? .030) 4.30 ? 4.50* (.169 ? .177) 1 3 4 5 6 7 8 9 10 detail a detail a is the part of the lead frame feature for reference only no measurement purpose 111214 13 6.40 ? 6.60* (.252 ? .260) 3.86 (.152) 2.74 (.108) 20 1918 17 16 15 1.20 (.047) max 0.05 ? 0.15 (.002 ? .006) 0.65 (.0256) bsc 0.195 ? 0.30 (.0077 ? .0118) typ 2 2.74 (.108) 0.45 0.05 0.65 bsc 4.50 0.10 6.60 0.10 1.05 0.10 3.86 (.152) millimeters (inches) *dimensions do not include mold flash. mold flash shall not exceed 0.150mm (.006") per side note: 1. controlling dimension: millimeters 2. dimensions are in 3. drawing not to scale see note 4 4. recommended minimum pcb metal size for exposed pad attachment 6.40 (.252) bsc fe package 20-lead plastic tssop (4.4mm) (reference ltc dwg # 05-08-1663 rev k) exposed pad variation cb detail a 0.60 (.024) ref 0.28 (.011) ref lt 8495 8495fa
32 for more information www.linear.com/lt8495 package description please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 4.00 0.10 note: 1. drawing is proposed to be made a jedec package outline mo-220 variation (wggd-1)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 2019 1 2 bottom view?exposed pad 2.00 ref 2.45 0.10 0.75 0.05 r = 0.115 typ r = 0.05 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf20) qfn 01-07 rev a recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.00 ref 2.45 0.05 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer 2.45 0.10 2.45 0.05 uf package 20-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1710 rev a) lt 8495 8495fa
33 for more information www.linear.com/lt8495 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number a 07/15 added qfn package option. added qfn package option and h-grade option in tssop. clarified quiescent current specifications. clarified rst leakage current specifications. added pin current and quiescent current graphs. clarified pin functions for qfn package. clarified leakage current characteristics in high temperature considerations. added new typical applications. 1 2, 3, 4, 9 3 4 8 9 23 30 lt 8495 8495fa
34 for more information www.linear.com/lt8495 ? linear technology corporation 2015 lt 0715 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/lt8495 related parts typical applications 450khz, wide input range 12v output sepic converter no load supply current efficiency ? ? v in 3v to 55v v in swen sw bias cpor cwdt c1, c3: 2.2f, 100v, x5r, 1210 c2: 10f, 25v, x5r, 1210 d1: onsemi mbra2h100 l1, l2: coiltronics drq125-100-r fb gnd wde lt8495 wdi rstin wdo rst ss rt c1 2.2f (v out ripple may increase below 6v v in ) c3 2.2f d1 l1 10h l2 10h v out 12v 0.2a (v in = 3v) 0.35a (v in = 4.5v) 0.65a (v in = 12v or higher) c2 10f 3 110k 8495 ta06 c 1m 3.09k 169k 1nf 1f 4.7nf 8495 ta06b 8495 ta06c part number description comments lt8494 70v, 2a boost/sepic 1.5mhz high efficiency dc/dc converter v in(min) = 2.5v, v in(max) = 32v, v out(min) = 70v, i q = 9a, i sd = <1a, 4mm 4mm qfn-20, tssop-20e packages lt3580 42v, 2a boost/inverting 2.5mhz high efficiency dc/dc converter v in : 2.5v to 32v, v out(max) = 40v, i q = 1ma, i sd < 1a, 3mm 3mm dfn-8, msop-8e packages lt 8580 65v, 1a boost/inverting dc/dc converter v in : 2.55v to 40v, v out(max) = 60v, i q = 1.2ma, i sd < 1a, 3mm 3mm dfn-8, msop-8e packages lt 8570/lt8570-1 65v, 500ma/250ma boost/inverting dc/dc converter v in(min) = 2.55v, v in(max) = 40v, v out(min) = 60v, i q = 1.2ma, i sd = <1a, 3 3 dfn-8, msop-8e package lt8582 40v, dual 3a, 2.5mhz high efficiency boost converter v in : 2.5v to 40v, v out(max) = 40v, i q = 2.8a, i sd < 1a, 7mm 4mm dfn-24 package lt 8471 40v, dual 3a, multitopology high efficiency dc/dc converter v in : 2.6v to 50v, v out(max) = 45v, i q = 2.4ma, i sd < 1a, tsop-20e package lt 3581 40v, 3.3a, 2.5mhz high efficiency boost converter v in : 2.5v to 40v, v out(max) = 40v, i q = 1ma, i sd < 1a, 4mm 3mm dfn-14, msop-16e packages lt 8582 40v, dual 3a boost, inverter, sepic, 2.5mhz high efficiency boost converter v in : 2.5v to 40v, v out(max) = 40v, i q = 2.1ma, i sd < 1a, 7mm 4mm dfn-24 package lt 3579/lt3579-1 40v, 3.3a boost, inverter, sepic, 2.5mhz high efficiency boost converter v in : 2.5v to 40v, v out(max) = 40v, i q = 1ma, i sd < 1a, 4mm 5mm qfn-20, tssop-20e packages lt 8495 8495fa 0.4 0.5 0.6 60 65 70 75 80 85 90 v in = 12v efficiency (%) watchdog enabled watchdog disabled input voltage (v) 0 10 20 30 40 50 v in = 24v 60 0 20 40 60 80 100 supply current (a) v in = 5v load current (a) 0.0 0.1 0.2 0.3

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